Inst 250 Final Assignment Overview


Computer Science 250: VLSI Systems Design

Fall 2010

Prof. John Wawrzynek

Prof. Krste Asanović

Dr. John Lazzaro

Lectures: Monday and Wednesday, 10:30AM-12:00PM, 320 Soda
Section: Thursday, 5:00PM-6:00PM, 310 Soda

Welcome to the Fall 2010 CS250 web page. More details to follow.


Detailed course info.
Handouts for CS250.
Papers for CS250.

Course Calendar with Handouts

Subject to Change.

WeekDateInstrLectureAssignments
1Mon Aug 30 JW Lecture 1: Course Introduction: History of VLSI in computer science. Early design representations and CAD, sIlicon foundry model, multi-project chips. Overview of course structure and student requirements. Lecture slides. Lab 1 out
Wed Sep 1 JW Lecture 2: VLSI Introduction. Chip-level alternatives: ASIC, FPGAs, full-custom, gate-array, via-programmable. IC Fabrication. RTL and other design representations. Quick tool flow overview. Lecture slides. 
Thur Sep 2 YL Section 1: Lab 1 & Tool Flow Overview. Section slides.  
2Mon Sep 6   Labor Day  
Wed Sep 8 JW Lecture 3: Physical Realities. Part I: Area & Timing. Circuit and wire-delay modeling. Circuit-level timing closure. Static timing tools. Lecture slides. 
Thur Sep 9 YL Section 2: Python scripting, Verilog coding guidelines. Section slides.  
3Mon Sep 13 JL Lecture 4: Physical Realities, Part II: Energy and power. Power consumption mechanisms. Power modeling and power-aware design overview. Power analysis tools. Power grid tools. Lecture slides. Lab 2 out
Lab 1 due (before class)
Wed Sep 15 All Paper Discussion: Papers 
Thur Sep 16 YL Section 3: Lab 2, RISC-V RTL Implementation and Synthesis. Optimizing your Register file. Section slides.  
4Mon Sep 20 JL Lecture 5: System Context: I/O signaling, Off-chip DRAM. Lecture slides. Lab 3 out
Tue Sep 21 YL Section 4: Optimizing your ALU. (Section moved for this week. Extended office hours on September 20th, Monday from 3pm to 5pm.) Section slides.  
Wed Sep 22 All Paper Discussion: Papers 
5Mon Sep 27 KA Lecture 6: Project details. Lecture slides. 
Wed Sep 29 KALecture 7: Overview of hardware design patterns. Lecture slides. 
Thur Sep 30 YL Section 5: Setup & Hold time violations. Common questions for Lab 2 and 3. Section slides.  
6Mon Oct 4 KA Lecture 8: Memory and Memory Design Patterns Lecture slides. Labs 2 & 3 due (before class)
Wed Oct 6 KA Lecture 9: Patterns for processing units and communication links. Lecture slides. 
Thur Oct 7 YL Section 6: Basics on IC Compiler, Discussion on RISC-V baseline processor. Project group discussions. No section slides.  
7Mon Oct 11 JL Lecture 10: Design verification strategies. Debugging. Unit testing. Regression suites. Lecture slides.Project Proposal due (before class)
Wed Oct 13 AllInitial project proposal presentations.  
Thur Oct 14 YL Office hours  
8Mon Oct 18 AllPrivate project meetings with groups. 
Mon Oct 18 YLOffice hours 
Wed Oct 20 AllPrivate project meetings with groups. 
9Mon Oct 25 AllPrivate project meetings with groups. 
Mon Oct 25YLOffice hours 
Wed Oct 27 AllPrivate project meetings with groups. 
10Mon Nov 1AllPublic group progress presentations. 
Mon Nov 1YLOffice hours 
Wed Nov 3AllPublic project progress presentations. 
11Mon Nov 8 AllPrivate project meetings with groups. 
Mon Nov 8YLOffice hours 
Wed Nov 10 AllPrivate project meetings with groups. 
12Mon Nov 15 AllPublic group progress presentations. 
Mon Nov 15YLOffice hours 
Wed Nov 17AllPublic group progress presentations. 
13Mon Nov 22AllPrivate project meetings with groups. 
Mon Nov 22YLOffice hours 
Wed Nov 24AllPrivate project meetings with groups. 
Thur Nov 25 Thanksgiving 
14Mon Nov 29AllFinal Project Presentations 
Wed Dec 1AllFinal Project Presentations 
15Tue Dec 7AllFinal Project Reports Due 6AM (No Extensions)  

Detailed course info.
How to set up accounts and tools for the labs.
More information about the project topics presented in lecture.
Handouts and other documentation you may find useful.

Course Calendar with Handouts
Subject to Change.

WeekDateInstrLectureAssignments
1Thu Aug 29JL Lecture 1: The Fab-Design Interface. Industry economics and organization. Manufacturing, from silica mine to packaged chip. Dennard scaling and Moore's Law. Chip design styles: structured custom, standard cells, logic synthesis, systems on a chip, programmable standard parts. Class project and schedule. Lecture slides.
2Tue Sep 3JB Lecture 2: Introduction to Chisel hardware description language. Background on hardware design history and comparison to Chisel. Quick Scala for Chiselers. Algebraic syntax, types and literals, combinational circuits, wires, ports, bundles, vecs, and registers. Simple two step RTL semantics with single clock domain. Lecture slides.Lab 1 out
Thu Sep 5JL Lecture 3: Timing. The GALS methodology. Combinational and clocked logic timing tutorial. Timing characterization of a new process. Pipelining, C-Slow retiming, and CLOS networks. Circuit details of flip-flops and inverters. Lecture slides.
3Tue Sep 10JL Lecture 4: Power and Energy. Overview of power issues in different product categoies. Transistor physics and the power wall. Design techniques: parallelism, power-down modes, multiple Vdds, clock gating, data-dependent processing, thermal management. Lecture slides.
Thu Sep 12JB Lecture 5: ParLab + Aspire + RISC-V + Rocket + Accelerators. Overview of ParLab and Aspire projects. ASPIRE solution of ensemble of parallel pattern-specific accelerators. Overview of RISC-V ISA. Introduction to Rocket single-issue in-order pipeline implementation of RISC-V. Overview of ROCC coprocessor interface. Lecture slides.Lab 2 out
Fri Sep 13 Lab 1 due
4Tue Sep 17 JL Lecture 6: Accelerator Projects. Power and energy techniques available for the project. Pareto optimality. The accelerator interface. Three worked project examples, and pointers to six other project ideas. Lecture slides.
Thu Sep 19JB Lecture 7: Chisel Part II. Conditional updates on wires, registers, and memories. Demystifying Chisel and placing Chisel in categories of hardware languages. ROMs and combinational, sequential, and single port memories. Abstraction through object orientation and functional programming. Modules construction and bulk wiring. Standard library of modules. Lecture slides.
5Tue Sep 24JL+JB Lecture 8: Design verification strategies and Chisel based testing. Lecture slides part 1 and part 2. Lab 2 due
Thu Sep 26JBLecture 9: Overview of hardware design patterns. Lecture slides
6Mon Sep 30JB Chisel Bootcamp @ Sutardja Dai Hall / 8:30a-5p -- info and registration
Tue Oct 1JL Lecture 10: Memory and memory design patterns. Lecture slidesLab 3 out
Thu Oct 3JB Lecture 11: Design patterns for processing units and communication links. Ready-valid interfaces. An overview of Lab 3. Lecture slides part 1, part 2, and part 3.
7Tue Oct 8All Oral Project Proposals Project
Proposals Due
Thu Oct 10All Oral Project Proposals
8Tue Oct 15All Private project meetings with groups. Lab 3 Due
Wed Oct 16Lab 4 out
Thu Oct 17AllPrivate project meetings with groups.
9Tue Oct 22AllPrivate project meetings with groups.
Thu Oct 24AllPrivate project meetings with groups.
Fri Oct 25 Lab 4 Due
10Tue Oct 29AllPublic project progress presentations.
Thu Oct 31AllPublic project progress presentations.
11Tue Nov 5AllPrivate project meetings with groups.
Thu Nov 7AllPrivate project meetings with groups.
12Tue Nov 12AllPrivate project meetings with groups.
Thu Nov 14AllPrivate project meetings with groups.
13Tue Nov 19AllPublic project progress presentations.
Thu Nov 21AllPrivate project meetings with groups.
14Tue Nov 26AllPrivate project meetings with groups.
Thu Nov 28AllThanksgiving
15Tue Dec 3AllPrivate project meetings with groups.
Thu Dec 5AllPrivate project meetings with groups.
16Fri Dec 13AllFinal Presentations from 9-11AM and 2-4PM in 380 Soda.
17Wed Dec 18AllFinal Project Reports due at 11:59PM (NO EXTENSIONS) .

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